ADuC7026 External Memory Interface Operation:

The ADuC7026 external memory interface consists of a multiplexed 16-bit address/data bus, the A16 line, and various control signals. The external memory interface is divided into four 128kB regions, each of which can individually be configured for 8-bit or 16-bit operation. In 16-bit operation, the A0 address bit is not needed. To free up the A16 line as an I/O pin, when configured for 16-bit operation the physical address bits A16:1 are driven onto the A15:0 lines. Each region has an external memory strobe (/MS3-/MS0) that is only active within the address space of that region, as shown below.

    /MS3    0x4000 0000 - 0x4001 FFFF
    /MS2    0x3000 0000 - 0x3001 FFFF
    /MS1    0x2000 0000 - 0x2001 FFFF
    /MS0    0x1000 0000 - 0x1001 FFFF

An example 8-bit external system that includes two 8-bit input ports and two 8-bit output ports is shown below. Note that the decoding logic uses some linear combination of the memory strobe, the read and write strobes, and the demultiplexed address bus.

Read Cycle
The basic read cycle signaling is illustrated below. Note that for an 8-bit reads the byte enables (BHE# and BLE#) can be ignored.

The basic read cycle timing can be modified by changing the settings in the XMxPAR registers, as shown below. The setting in XMxPAR[7:4] lengthens the assertion of the read strobe (RS#), and is the most commonly implemented type of wait state.

The basic write cycle signaling is illustrated below. Note that for an 8-bit writes the byte enables (BHE# and BLE#) can be ignored.

The basic write cycle timing can be modified by changing the settings in the XMxPAR registers, as shown below. The setting in XMxPAR[7:4] lengthens the assertion of the write strobe (WS#), and is the most commonly implemented type of wait state.

Copyright © College of Engineering, University of Wisconsin-Madison Content By: morrow@engr.wisc.edu