Testing the ADuC7026-Cyclone Development Board:

To test the ADuC7026-Cyclone development board, you need to use Quartus to configure the FPGA, and use Keil uVision to program the ADuC7026 with the project below (there is no source code, but you can run the debugger with just the executable file). Both are in ZIP format.

• Quartus project
• Keil uVision project

Configure the FPGA, then load and run the Keil project. (Refer to the FPGA schematic for connection information.)

When the ADuC7026 initially starts running, it does a loopback test on the GPIO pins that are not otherwise used in the test. These pins are simply connected directly through the FPGA. The lines are tested by walking a single 1 bit through the GPIO pins, with P4.7-P4.0, P1.4-P1.2 used as outputs and P3.7-P3.0, P1.7-P1.5 used as inputs. The test starts by driving the 1 on P4.7 and goes through the pins in the order shown  in the table below. If the test fails, it stops with a single 1 driven on the line where a problem was first detected.  (Note that an input that is read as a 1 when it should be a 0 will also cause the test to halt.)

If the loopback test is successful, the ADuC7026 automatically advances to its initial program loop to test the 7-segment LED displays. In this mode it sequentially illuminates just a single segment of a single display. The segment is illuminated on the displays from left to right, then the process repeats with the next segment illuminated. LED bar segment 9 (leftmost) flashes at approximately 1 Hz to indicate that the processor successfully completed the GPIO loopback test. The ADuC7026 will remain in this mode until either PB1 or PB2 are pressed.

Once PB1 or PB2 are pressed, the ADuC7026 enters and remains in the main test loop. In this mode, the following can be observed;

• LED bar segment 9 (leftmost) continues to flash at 1 Hz.
• If PB1 is not pressed, LED bar segment 8 flashes at 5.0 Hz to indicate that the 20MHz external clock (CLK1) is active. LED bar segments 7-0 mirror the current positions of the DIP switch 7-0.
• If PB1 is pressed, LED bar segment 8 flashes at 10.4 Hz to indicate that the 41.78MHz clock from the ADuC7026 to the FPGA (CLK0_ARM) is active. LED bar segments 2-0 mirror the state of the rotary encoder outputs.
• Audio loopback - the ADC3/2 analog inputs (line level input) are sampled at 10kHz and driven out on DAC1/0 analog outputs (line level output).
• DAC3/2 analog outputs drive 0-2.5V ramp waveforms of opposite polarity at a 10kHz sample rate.
• ADC input values are displayed on the 7-segment displays in the format N.XXX, where XXX is the hex value read on ADC channel number N (if N > 0xB, the actual channel number displayed is N+4). The ADC channel is sample at 10kHz and averaging is used to smooth the display results. Press and release PB2 to advance the ADC channel number.
• If a keypad is connected, pressing any key on the keypad will cause the corresponding ADC channel to be displayed.
• Serial data at 38.4kbaud, 8-data, no parity, 1-stop is echoed back on the serial port connection. (Ensure the jumpers are installed on JP4 properly, and set the terminal program for no flow control.)
• If a motor control board is connected to J5, the motor will rotate clockwise if PB1 is pressed and counterclockwise if PB2 is pressed. The motor current control is set by DIP switch SW7:6, as shown below. While PB1 is pressed, LED bar segment 7 shows the optical sensor output from the motor module.

Copyright © College of Engineering, University of Wisconsin-Madison Content By: morrow@engr.wisc.edu